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What is a chip worth?
Skyphos lets researchers side-step delays and test ideas the week of inspiration.
- Submit drawings in 2D or 3D format via most drawing platforms (AutoDesk, SolidWorks, Sketch-Up, Rhino 3d etc.)
- 10 re-usable chips delivered in days (10 chips of one design - or 1 chip of 10 designs)
- No mold costs, no change over costs, ever.
- Discounts based on total chips ordered per lab/year
- Choose between sealed single layer, open top (with closure kit), multi-layer monocoque
- Artifacts down to 20 um XY and 200 um in height
- Channels down to 30 um width
Ready to test real time?
Order one of our printers for your lab and select from one of our three resins to best suit your needs. We have both academic and research based discounts available. Our printers are easy to use, come assembled and aligned. We get you printing in 30 minutes - first chips that day.
What do chips cost?
On average, about $1 worth of material is wrapped up in a prototype PDMS chip, but is this the true cost? That $1 doesn't include mask and master charges, wait time, overhead for keeping the lights on at the lab, student/technician time, specialized chemicals and dedicated lab space to perform SU-8. It doesn't account for these time losses compounded over development phase to get to publication or trials. It doesn't account for mistakes of positive/negative masks, or the difficulty and failure rates assembling multi-layer chip.
If on average, it takes 3-5 iterations to optimize a design, this means the projected timeline is slowed by months. Only a few days to weeks are spent working with the actual experiments that deliver data to drive decision from each revision. In Process Engineering calls this: "Non-Value Add". The customer (researchers or end-user) does not care about the time spent making the chip, the time waiting for a new mold, the lab maintenance, etc.
The hidden costs of PDMS costs investigators time and money:
- A new design for PDMS molded chips costs, on average, 6 weeks and $600
- Masks $50 and 1 week
- Each chip takes about 1-1.5 hours per layer to cure, assemble and port
- Multi-layer designs add complexity and time and failure opportunities
- The process and materials place limits on aspect ratios, (base:height is 1:2)
- 2D planar designs limit surface area and signal to noise
- Molds for hot embossing and hot injection are a huge investment
- Moving to production adds issues with materials and surface interactions
Every lab faces these issues because everyone uses the same processes. Over the past 20+ years, the microfluidics community has relied on lithographic techniques appropriated from the semi-conductor industry.